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INTEGRATED CIRCUITS
DATA SHEET
SAA7120; SAA7121 Digital Video Encoder (ConDENC)
Preliminary specification File under Integrated Circuits, IC22 1997 Jan 06
Philips Semiconductors
Preliminary specification
Digital Video Encoder (ConDENC)
FEATURES * Monolithic CMOS 3.3 V (5 V) device * Digital PAL/NTSC encoder * System pixel frequency 13.5 MHz * Accepts MPEG decoded data on 8-bit wide input port; input data format Cb-Y-Cr (CCIR 656), SAV and EAV * Three DACs for Y, C and CVBS, two times oversampled with 10 bit resolution * Real time control of subcarrier * Cross colour reduction filter * Closed captioning encoding and WST- and NABTS-Teletext encoding including sequencer and filter * Line 23 wide screen signalling encoding * Fast I2C-bus control port (400 kHz) * Encoder can be master or slave * Programmable horizontal and vertical input synchronization phase * Programmable horizontal sync output phase * Internal colour bar generator (CBG) * 2 x 2 bytes in lines 20 (NTSC) for copy guard management system can be loaded via I2C-bus * Down-mode of DACs * Controlled rise/fall times of synchronization and blanking output signals QUICK REFERENCE DATA SYMBOL VDDA VDDD IDDA IDDD Vi Vo(p-p) RL ILE DLE Tamb analog supply voltage digital supply voltage analog supply current digital supply current input signal voltage levels analog output signal voltages Y, C, and CVBS without load (peak-to-peak value) load resistance LF integral linearity error LF differential linearity error operating ambient temperature 1.2 75 - - 0 PARAMETER
SAA7120; SAA7121
* Macrovision Pay-per-View copy protection system rev.7 and rev.6.1 as option. This applies to SAA7120 only. The device is protected by USA patent numbers 4631603, 4577216 and 4819098 and other intellectual property rights. Use of the Macrovision anti-copy process in the device is licensed for non-commercial home use only. Reverse engineering or disassembly is prohibited. Please contact your nearest Philips Semiconductors sales office for more information. * QFP44 package. GENERAL DESCRIPTION The SAA7120; SAA7121 encodes digital YUV video data to an NTSC or PAL CVBS or S-Video signal. The circuit accepts CCIR compatible YUV data with 720 active pixels per line in 4 : 2 : 2 multiplexed formats, for example MPEG decoded data. It includes a sync/clock generator and on-chip DACs.
MIN. 3.1 3.0 - -
TYP. 3.3 3.3 - - 1.35 - - - -
MAX. 3.5 3.6 62 38 1.45 300 3 1 +70
UNIT V V mA mA V LSB LSB C
TTL compatible
1997 Jan 06
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Philips Semiconductors
Preliminary specification
Digital Video Encoder (ConDENC)
ORDERING INFORMATION TYPE NUMBER SAA7120; SAA7121 BLOCK DIAGRAM PACKAGE NAME QFP44 DESCRIPTION
SAA7120; SAA7121
VERSION SOT307-2
plastic quad flat package; 44 leads (lead length 2.35 mm); body 10 x 10 x 1.75 mm
handbook, full pagewidth
VDDA1, RCV1 TTXRQ XTALO XCLK LLC VDDA2, VDDA3 VDDA4 RCV2 XTALI
RESET SDA SCL SA 40 42 41 21
7
8
43 37 34 35 4
25, 28, 31
36
I2C-BUS INTERFACE I2C-bus control
SAA7120 SAA7121
SYNC CLOCK I2C-bus control
clock and timing Y Y ENCODER CbCr C
MP7 to MP0
9 to 16 DATA MANAGER
30 OUTPUT INTERFACE D A 27 24
CVBS Y C
I2C-bus control TTX 44 I2C-bus control
I2C-bus control 32, 33 VSSA1 VSSA2
5, 18, 38 VSSD1, VSSD2, VSSD3
6, 17, 39 VDDD1, VDDD2, VDDD3
1, 20, 22, 23, 26, 29 res.
19 RTCI
2 SP
3
MBH787
AP
Fig.1 Block diagram.
1997 Jan 06
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Philips Semiconductors
Preliminary specification
Digital Video Encoder (ConDENC)
PINNING SYMBOL res. SP AP LLC VSSD1 VDDD1 RCV1 RCV2 MP7 MP6 MP5 MP4 MP3 MP2 MP1 MP0 VDDD2 VSSD2 RTCI res. SA res. res. C VDDA1 res. Y VDDA2 res. CVBS VDDA3 VSSA1 VSSA2 XTALO XTALI VDDA4 XCLK PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 I/O - I I I I I I/O I/O I I I I I I I I I I I - I - - O I - O I - O I I I O I I O digital supply voltage 2 digital ground 2 reserved DESCRIPTION
SAA7120; SAA7121
test pin; connected to digital ground for normal operation test pin; connected to digital ground for normal operation line-locked clock; this is the 27 MHz master clock for the encoder digital ground 1 digital supply voltage 1 raster control 1 for video port; this pin receives/provides a VS/FS/FSEQ signal raster control 2 for video port; this pin provides an HS pulse of programmable length or receives an HS pulse
MPEG port; it is an input for "CCIR 656" style multiplexed Cb Y, Cr data
Real Time Control input; if the LLC clock is provided by an SAA7111 or SAA7151B, RTCI should be connected to pin RTCO of the decoder to improve the signal quality reserved the I2C-bus slave address select input pin; LOW: slave address = 88H, HIGH = 8CH reserved reserved analog output of the chrominance signal analog supply voltage 1 for the C DAC reserved analog output of VBS signal analog supply voltage 2 for the Y DAC reserved analog output of the CVBS signal analog supply voltage 3 for the CVBS DAC analog ground 1 for the DACs analog ground 2 for the oscillator and reference voltage crystal oscillator output (to crystal) crystal oscillator input (from crystal); if the oscillator is not used, this pin should be connected to ground analog supply voltage 4 for the oscillator and reference voltage clock output of the crystal oscillator
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Philips Semiconductors
Preliminary specification
Digital Video Encoder (ConDENC)
SAA7120; SAA7121
SYMBOL VSSD3 VDDD3 RESET SCL SDA TTXRQ TTX
PIN 38 39 40 41 42 43 44
I/O I I I I I/O O I digital ground 3 digital supply voltage 3
DESCRIPTION
reset input, active LOW; after reset is applied, all digital I/Os are in input mode; the I2C-bus receiver waits for the START condition I2C-bus serial clock input I2C-bus serial data input/output teletext request output, indicating when bit stream is valid teletext bit stream input
39 VDDD3
43 TTXRQ
36 VDDA4
40 RESET
38 VSSD3
35 XTALI
37 XCLK
handbook, full pagewidth
34 XTALO
42 SDA
41 SCL
44 TTX
res. 1 SP 2 AP 3 LLC 4 VSSD1 5 VDDD1 6 RCV1 7 RCV2 8 MP7 9 MP6 10 MP5 11
33 VSSA2 32 VSSA1 31 VDDA3 30 CVBS 29 res.
SAA7120 SAA7121
28 VDDA2 27 Y 26 res. 25 VDDA1 24 C 23 res.
MP4 12
MP3 13
MP2 14
MP1 15
MP0 16
VDDD2 17
VSSD2 18
RTCI 19
res. 20
SA 21
res. 22
MBH790
Fig.2 Pin configuration.
1997 Jan 06
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Philips Semiconductors
Preliminary specification
Digital Video Encoder (ConDENC)
FUNCTIONAL DESCRIPTION The digital video encoder (ConDENC) encodes digital luminance and colour difference signals simultaneously into analog CVBS and S-Video signals. NTSC-M, PAL B/G, and sub-standards are supported. Both interlaced and non-interlaced operation is possible for all standards. The basic encoder function consists of subcarrier generation, colour modulation and the insertion of synchronization signals. Luminance and chrominance signals are filtered in accordance with the standard requirements of "RS-170-A" and "CCIR 624". For ease of analog post-filtering the signals are oversampled twice with respect to the pixel clock prior to digital-to-analog conversion. The filter characteristics are shown in Figs 3 and 4. The DACs for Y, C, and CVBS have 10-bit resolution. The 8-bit multiplexed Cb-Y-Cr formats are "CCIR 656" (D1 format) compatible, but the SAV and EAV codes can
SAA7120; SAA7121
be decoded optionally when the device is to operate in slave mode. It is also possible to connect a Philips Digital Video Decoder (SAA7111 or SAA7151B) to the ConDENC. Via pin RTCI, connected to RTCO of a decoder, information concerning the actual subcarrier, PAL-ID and (if used in conjunction with the SAA7111) the subcarrier phase can be inserted. The ConDENC synthesizes all necessary internal signals, colour subcarrier frequency and synchronization signals. Wide screen signalling data can be loaded via the I2C-bus. It is inserted into line 23 for 50 Hz field rate standards. The IC contains closed caption and extended data services encoding (line 21), and supports anti-taping signal generation in accordance with Macrovision. Possibilities are provided for setting video parameters: Black and blanking level control Colour subcarrier frequency Variable burst amplitude.
Gv handbook, full pagewidth (dB) 0 -6 -12 -18 -24 -30 -36 -42 -48 -54 0 2 4 6 8 10 12 f (MHz) 14
(4) (2) (3) (1)
6
MGD672
(1) CCRS1 = 0; CCRS0 = 1. (2) CCRS1 = 1; CCRS0 = 0.
(3) CCRS1 = 0; CCRS0 = 0. (4) CCRS1 = 1; CCRS0 = 1.
Fig.3 Luminance transfer characteristic 1.
1997 Jan 06
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Philips Semiconductors
Preliminary specification
Digital Video Encoder (ConDENC)
SAA7120; SAA7121
During reset (RESET = LOW) and after reset is released, all digital I/O stages are set to input mode. A reset forces the I2C-bus interface to abort a running bus transfer and sets register 3A to 03H, register 61 to 06H, registers 6BH and 6EH to 00H and bit TTX60 to 0. All other control registers are not influenced by a reset. Encoder VIDEO PATH The encoder generates out of Y, U and V baseband signals luminance and colour subcarrier output signals, suitable for use as CVBS or separate Y and C signals. Luminance is modified in gain and in offset (the latter programmable in a certain range to enable different black level set-ups). A fixed synchronization level in accordance with standard composite synchronization schemes is inserted. The inserted blanking level is programmable to allow for manipulations with Macrovision anti-taping. Additional insertion of AGC super-white pulses, programmable in height, is supported.
handbook, halfpage
MBE736
1
Gv (dB) 0
(1)
-1 -2
-3 -4 -5
0
2
4
f (MHz)
6
(1) CCRS1 = 0; CCRS0 = 0.
Fig.4 Luminance transfer characteristic 2.
handbook, full pagewidth 6
MBE737
Gv
(dB)
0 -6
-12 -18 -24
(1) (2)
-30 -36 -42 -48 -54 0 2 4 6 8 10 12 f (MHz) 14
(1) SCBW = 1. (2) SCBW = 0.
Fig.5 Chrominance transfer characteristic 1.
1997 Jan 06
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Philips Semiconductors
Preliminary specification
Digital Video Encoder (ConDENC)
SAA7120; SAA7121
signal TTXRQ a single teletext bit has to be provided after a programmable delay at input pin.
handbook, halfpage
2
MBE735
Gv (dB) 0
(1)
Phase variant interpolation is achieved on this bitstream in the internal teletext encoder, providing sufficient small phase jitter on the output text lines. TTXRQ provides a fully programmable request signal to the teletext source, indicating the insertion period of bitstream at lines selectable independently for both fields. The internal insertion window for text is set to 360 (PAL-WST), 296 (NTSC-WST) or 288 (NABTS) teletext bits including clock run-in bits. For protocol and timing see Fig.7. CLOSED CAPTION ENCODER
(2)
-2
-4
-6
0
0.4
0.8
1.2 f (MHz) 1.6
(1) SCBW = 1. (2) SCBW = 0.
Fig.6 Chrominance transfer characteristic 2.
Using this circuit, data in accordance with the specification of closed caption or extended data service, delivered by the control interface, can be encoded (Line 21). Two dedicated pairs of bytes (two bytes per field), each pair preceded by run-in clocks and framing code, are possible. The actual line number where data is to be encoded in, can be modified in a certain range.
In order to enable easy analog post-filtering, luminance is interpolated from 13.5 MHz data rate to 27 MHz data rate, providing luminance in 10-bit resolution. This filter is also used to define smoothed transients for synchronization pulses and blanking period. For transfer characteristic of the luminance interpolation filter see Figs 3 and 4. Chrominance is modified in gain (programmable separately for U and V), standard dependent burst is inserted, before baseband colour signals are interpolated from 6.75 MHz data rate to 27 MHz data rate. One of the interpolation stages can be bypassed, thus providing a higher colour bandwidth, which can be made use of for Y and C output. For transfer characteristics of the chrominance interpolation filter see Figs 5 and 6. The amplitude, beginning and ending of inserted burst is programmable in a certain range, suitable for standard signals and for special effects. Behind the succeeding quadrature modulator, colour in 10-bit resolution is provided on subcarrier. The numeric ratio between Y and C outputs is in accordance with set standards. TELETEXT INSERTION AND ENCODING Pin TTX receives a WST- or NABTS-Teletext bitstream sampled at the LLC clock. At each rising edge of output
Data clock frequency is in accordance with definition for NTSC-M standard 32 times horizontal line frequency. Data LOW at the output of the DACs corresponds to 0 IRE, data HIGH at the output of the DACs corresponds to approximately 50 IRE. It is also possible to encode Closed Caption Data for 50 Hz field frequencies at 32 times horizontal line frequency. ANTI-TAPING (SAA7120 ONLY) For more information contact your nearest Philips Semiconductors sales office. Data manager In the data manager, real time arbitration on the data stream to be encoded is performed. A pre-defined colour look-up table located in this block can be read out in a pre-defined sequence (8 steps per active video line), achieving a colour bar test pattern generator without the need for an external data source. The colour bar function is under software control only. Output interface/DACs In the output interface encoded Y and C signals are converted from digital to analog in 10-bit resolution.
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Philips Semiconductors
Preliminary specification
Digital Video Encoder (ConDENC)
Y and C signals are also combined to a 10-bit CVBS signal. The CVBS output occurs with the same processing delay as the Y and C outputs. Absolute amplitude at the input of the DAC for CVBS is reduced by 1516 with respect to Y and C DACs to make maximum use of conversion ranges. Outputs of the DACs can be set together in two groups via software control to minimum output voltage for either purpose. Synchronization Synchronization of the ConDENC is able to operate in two modes; slave mode and master mode. In the slave mode, the circuit accepts synchronization pulses at the bidirectional RCV1 port. The timing and trigger behaviour related to RCV1 can be influenced by programming the polarity and the on-chip delay of RCV1. Active slope of RCV1 defines the vertical phase and optionally the odd/even and colour frame phase to be initialized, it can be also used to set the horizontal phase. If the horizontal phase is not to be influenced by RCV1, a horizontal synchronization pulse needs to be supplied at the pin RCV2. Timing and trigger behaviour can also be influenced by RCV2. If there are missing pulses at RCV1 and/or RCV2, the time base of ConDENC runs free, thus an arbitrary number of synchronization slopes may be absent, but no additional pulses (with the incorrect phase) must occur. If the vertical and horizontal phase is derived from RCV1, RCV2 can be used for horizontal or composite blanking input or output. Alternatively, the device can be triggered by auxiliary codes in a "CCIR 656" data stream at the MP port. In the master mode, the time base of the circuit continuously runs free. On the RCV1 port, the device can output: * A Vertical Synchronisation signal (VS) with 3 or 2.5 lines duration, or * An ODD/EVEN signal which is LOW in odd fields, or * A field sequence signal (FSEQ) which is HIGH in the first of 4 or 8 fields respectively.
SAA7120; SAA7121
On the RCV2 port, the device can provide a horizontal synchronization pulse with programmable start and stop phase; this pulse can be inhibited in the vertical blanking period to build up, for example, a composite blanking signal. The polarity of both RCV1 and RCV2 is selectable by software control. The length of a field and the start and end of its active part can be programmed. The active part of a field always starts at the beginning of a line. Teletext timing The teletext timing is shown in Fig.7. tFD is the time needed to interpolate input data TTX and inserting it into the CVBS and Y output signal, such that it appears at tTTX = 10.2 s (PAL) or tTTX = 10.5 s (NTSC) after the leading edge of the horizontal synchronization pulse. Time tPD is the pipeline delay time introduced by the source that is gated by TTXRQ in order to deliver TTX data. This delay is programmable by register TTXHD. For every active HIGH-state at output pin TTXRQ, a new teletext bit must be provided by the source. Since the beginning of the pulses representing the TTXRQ signal and the delay between the rising edge of TTXRQ and valid teletext input data are fully programmable (TTXHS and TTXHD), the TTX data is always inserted at the correct position after the leading edge of outgoing horizontal synchronization pulse. Time tTTXWin is the internally used insertion window for TTX data; it has a constant length that allows insertion of 360 teletext bits at a text data rate of 6.9375 Mbits/s (PAL), 296 teletext bits at a text data rate of 5.7272 Mbits/s (World Standard TTX) or 288 teletext bits at a text data rate of 5.7272 Mbits/s (NABTS). The insertion window is not opened if the control bit TTXEN is logic 0. Using appropriate programming, all suitable lines of the odd field (TTXOVS and TTXOVE) plus all suitable lines of the even field (TTXEVS and TTXEVE) can be used for teletext insertion.
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Philips Semiconductors
Preliminary specification
Digital Video Encoder (ConDENC)
SAA7120; SAA7121
handbook, full pagewidth
CVBS/Y tTTX textbit #: TTX 1 2 3 4 5 6 7 8 9 10 11 12 tTTXWin 13 14 15 16 17 18 19 20 21 22 23 24
tPD
tFD
TTXRQ
MBH788
Fig.7 Teletext timing.
Analog output voltages The analog output voltages are dependent on the open-loop voltage of the operational amplifiers for full-scale conversion (typical value 1.35 V), the internal series resistor (typical value 2 ), the external series resistor and the external load impedance. The digital output signals in front of the DACs under nominal conditions occupy different conversion ranges, as indicated in Table 1 for a 100100 colour bar signal. Values for the external series resistors result in a 75 load. Input levels and formats The ConDENC expects digital Y, Cb, Cr data with levels (digital codes) in accordance with "CCIR 601" (see Tables 2 and 3). For C and CVBS outputs, deviating amplitudes of the colour difference signals can be compensated by independent gain control setting, while gain for luminance is set to predefined values, distinguishable for 7.5 IRE set-up or without set-up. Reference levels are measured with a colour bar, 100% white, 100% amplitude and 100% saturation.
Table 1
Digital output signals conversion range
CONVERSION RANGE (peak-to-peak) (digits) CVBS, SYNC TIP-TO-PEAK CARRIER 1016 Table 2 Y (VBS) SYNC TIP-TO-WHITE 881
"CCIR 601" signal component levels
SIGNALS
COLOUR Y White Yellow Cyan Green Magenta Red Blue Black 235 210 170 145 106 81 41 16 Cb 128 16 166 54 202 90 240 128 Cr 128 146 16 34 222 240 110 128
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Philips Semiconductors
Preliminary specification
Digital Video Encoder (ConDENC)
I2C-bus interface The I2C-bus interface is a standard slave transceiver, supporting 7-bit slave addresses and 400 kbits/s guaranteed transfer rate. It uses 8-bit subaddressing with an auto-increment function. All registers are write only, except one readable status byte. Two I2C-bus slave addresses are present: 88H: LOW at pin SA 8CH: HIGH at pin SA. Table 3 8-bit multiplexed format (similar to "CCIR 601") BITS 0 Sample Luminance pixel number Colour pixel number Table 4 S Table 5 I2C-bus address format; see Table 5 SLAVE ADDRESS ACK SUBADDRESS ACK DATA 0 ACK Cb0 0 0 1 Y0 2 Cr0 1 2 Y1 4 Cb2 2
SAA7120; SAA7121
Tables 5 and 4 summarize the format of the I2C-bus addressing. For more information on how to use the I2C-bus see "The I2C-bus and how to use it", order no. 9398 393 40011. Tables 7 to 42 contain the programming information for the subaddresses. Table 6 summarises this information.
5 Y2 2
6 Cr2 3
7 Y3
--------
DATA n
ACK
P
Explanation of Table 4 DESCRIPTION START condition 1 0 0 0 1 0 0 x or 1 0 0 0 1 1 0 x (1) acknowledge, generated by the slave subaddress byte data byte continued data bytes and ACKs STOP condition
PART S Slave address ACK Subaddress(2) DATA -------P Notes 1. x is the read/write control bit; write: x = logic 0; read: x = logic 1, no subaddressing with read.
2. If more than 1 byte DATA is transmitted, then auto-increment of the subaddress is performed.
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11
Table 6 DATA BITS(1) D7 0 0 WSS7 WSSON DECCOL 0 CGO07 CGO17 CGE07 CGE17 CGEN1 0 0 CBENB CHPS7 GAINU7 GAINV7 GAINU8 GAINV8 CCRS1 0 0 RTCE FSC07 FSC15 FSC23 BSTA6 FSC06 FSC14 FSC22 DOWN 0 0 INPI BSTA5 FSC05 FSC13 FSC21 CCRS0 BLNVB5 DECPH BLNNL5 DECOE BLCKL5 GAINV6 GAINV5 GAINV4 BLCKL4 BLNNL4 BLNVB4 0 YGS BSTA4 FSC04 FSC12 FSC20 GAINU6 GAINU5 GAINU4 CHPS6 CHPS5 CHPS4 0 0 SYMP 0 CHPS3 GAINU3 GAINV3 BLCKL3 BLNNL3 BLNVB3 0 0 BSTA3 FSC03 FSC11 FSC19 0 0 0 0 0 0 0 0 0 0 0 CHPS2 GAINU2 GAINV2 BLCKL2 BLNNL2 BLNVB2 0 SCBW BSTA2 FSC02 FSC10 FSC18 CGEN0 0 0 0 0 CGE16 CGE15 CGE14 CGE13 CGE12 CGE06 CGE05 CGE04 CGE03 CGE02 CGO16 CGO15 CGO14 CGO13 CGO12 CGO06 CGO05 CGO04 CGO03 CGO02 CGO01 CGO11 CGE01 CGE11 0 0 0 Y2C CHPS1 GAINU1 GAINV1 BLCKL1 BLNNL1 BLNVB1 0 PAL BSTA1 FSC01 FSC09 FSC17 0 BE5 BE4 BE3 BE2 BE1 DECFIS BS5 BS4 BS3 BS2 BS1 0 WSS13 WSS12 WSS11 WSS10 WSS9 WSS8 BS0 BE0 CGO00 CGO10 CGE00 CGE10 0 0 0 UV2C CHPS0 GAINU0 GAINV0 BLCKL0 BLNNL0 BLNVB0 0 FISE BSTA0 FSC00 FSC08 FSC16 WSS6 WSS5 WSS4 WSS3 WSS2 WSS1 WSS0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D6 D5 D4 D3 D2 D1 D0
Slave receiver (slave address 88H or 8CH)
1997 Jan 06
REGISTER FUNCTION
SUB ADDRESS
Null
00
Philips Semiconductors
Null
25
Wide screen signal
26
Wide screen signal
27
Real time control, Burst start
28
Burst end
29
Copy guard odd 0
2A
Copy guard odd 1
2B
Copy guard even 0
2C
Copy guard even 1
2D
Digital Video Encoder (ConDENC)
Copy guard enable
2E
Null
2F
12
Null
39
Input port control
3A
Chrominance phase
5A
Gain U
5B
Gain V
5C
Gain U MSB, Real time control, Black level
5D
Gain V MSB, Real time control, Blanking level
5E
CCR, Blanking level VBI
5F
Null
60
Standard control
61
RTC enable, Burst amplitude
62
Subcarrier 0
63
Subcarrier 1
64
SAA7120; SAA7121
Preliminary specification
Subcarrier 2
65
DATA BITS(1) D7 FSC31 L21O07 L21O17 L21E07 L21E17 SRCV11 HTRIG7 HTRIG10 SBLBN CCEN1 RCV2S7 RCV2E7 0 TTXHS7 TTXHD7 0 TTXOVS7 TTXOVE7 TTXEVS7 TTXEVE7 FAL7 LAL7 TTX60 0 LINE12 LINE20 LINE19 LINE11 0 0 LINE10 LINE18 LAL8 0 LAL6 LAL5 FAL6 FAL5 TTXEVE6 TTXEVE5 FAL4 LAL4 FAL8 0 LINE9 LINE17 TTXEVS6 TTXEVS5 TTXEVS4 TTXEVE4 TTXOVE6 TTXOVE5 TTXOVE4 TTXOVS6 TTXOVS5 TTXOVS4 0 0 0 0 TTXOVS3 TTXOVE3 TTXEVS3 TTXEVE3 FAL3 LAL3 TTXEVE8 0 LINE8 LINE16 TTXHD6 TTXHD5 TTXHD4 TTXHD3 TTXHS6 TTXHS5 TTXHS4 TTXHS3 RCV2E10 RCV2E9 RCV2E8 0 RCV2E6 RCV2E5 RCV2E4 RCV2E3 RCV2E2 RCV2S10 TTXHS2 TTXHD2 VS_S2 TTXOVS2 TTXOVE2 TTXEVS2 TTXEVE2 FAL2 LAL2 TTXOVE8 0 LINE7 LINE15 RCV2S6 RCV2S5 RCV2S4 RCV2S3 RCV2S2 CCEN0 TTXEN SCCLN4 SCCLN3 SCCLN2 0 PHRES1 PHRES0 0 0 FLC1 SCCLN1 RCV2S1 RCV2E1 RCV2S9 TTXHS1 TTXHD1 VS_S1 TTXOVS1 TTXOVE1 TTXEVS1 TTXEVE1 FAL1 LAL1 TTXEVS8 0 LINE6 LINE14 HTRIG9 HTRIG8 VTRIG4 VTRIG3 VTRIG2 VTRIG1 HTRIG6 HTRIG5 HTRIG4 HTRIG3 HTRIG2 HTRIG1 SRCV10 TRCV2 ORCV1 PRCV1 CBLF ORCV2 PRCV2 HTRIG0 VTRIG0 FLCO SCCLN0 RCV2S0 RCV2E0 RCV2S8 TTXHS0 TTXHD0 VS_S0 TTXOVS0 TTXOVE0 TTXEVS0 TTXEVE0 FAL0 LAL0 TTXOVS8 0 LINE5 LINE13 L21E16 L21E15 L21E14 L21E13 L21E12 L21E11 L21E10 L21E06 L21E05 L21E04 L21E03 L21E02 L21E01 L21E00 L21O16 L21O15 L21O14 L21O13 L21O12 L21O11 L21O10 L21O06 L21O05 L21O04 L21O03 L21O02 L21O01 L21O00 FSC30 FSC29 FSC28 FSC27 FSC26 FSC25 FSC24 D6 D5 D4 D3 D2 D1 D0
REGISTER FUNCTION
SUB ADDRESS
1997 Jan 06
Subcarrier 3
66
Line 21 odd 0
67
Line 21 odd 1
68
Philips Semiconductors
Line 21 even 0
69
Line 21 even 1
6A
RCV port control
6B
Trigger control
6C
Trigger control
6D
Multi control
6E
Closed caption, Teletext enable
6F
RCV2 output start
70
Digital Video Encoder (ConDENC)
RCV2 output end
71
MSBs RCV2 output
72
13
TTX request H start
73
TTX request H delay
74
V-Sync shift
75
TTX odd request V S
76
TTX odd request V E
77
TTX even request V S
78
TTX even request V E
79
First active line
7A
Last active line
7B
MSB vertical
7C
Null
7D
Disable TTX line
7E
Disable TTX line
7F
Note
SAA7120; SAA7121
Preliminary specification
1. All bits labelled `0' are reserved. They must be programmed with logic 0.
Philips Semiconductors
Preliminary specification
Digital Video Encoder (ConDENC)
Slave Receiver Table 7 Subaddress 26 and 27 LOGIC LEVEL - wide screen signalling bits: DESCRIPTION 13 to 11 = reserved 10 to 8 = subtitles
SAA7120; SAA7121
DATA BYTE WSS
7 to 4 = enhanced services 3 to 0 = aspect ratio WSSON 0 1 Table 8 wide screen signalling output is disabled wide screen signalling output is enabled
Subaddress 28 and 29 LOGIC LEVEL - - 0 1 0 1 DESCRIPTION starting point of burst in clock cycles ending point of burst in clock cycles disable colour detection bit of RTCI input enable colour detection bit of RTCI input field sequence as FISE in subaddress 61 field sequence as FISE bit in RTCI input bit RTCE must be set to 1 (see Fig.10) bit RTCE must be set to 1 (see Fig.10) REMARKS PAL : BS = 33 (21H) NTSC : BS = 25 (19H) PAL : BS = 29 (1DH) NTSC : BS = 29 (1DH)
DATA BYTE BS BE DECCOL DECFIS
Table 9
Subaddress 2A to 2D DESCRIPTION first byte of Copy guard data, odd field second byte of Copy guard data, odd field first byte of Copy guard data, even field second byte of Copy guard data, even field REMARKS LSBs of the respective bytes are encoded immediately after run-in and framing code, the MSBs of the respective bytes have to carry the parity bit, in accordance with the definition of Line 20 encoding format.
DATA BYTE CGO0 CGO1 CGE0 CGE1
Table 10 Subaddress 2E DATA BYTE DESCRIPTION CCEN1 0 0 1 1 CCEN0 0 1 0 1 copy guard encoding off enables encoding in field 1 (odd) enables encoding in field 2 (even) enables encoding in both fields
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Philips Semiconductors
Preliminary specification
Digital Video Encoder (ConDENC)
Table 11 Subaddress 3A DATA BYTE UV2C Y2C SYMP CBENB LOGIC LEVEL 0 1 0 1 0 1 0 1 Table 12 Subaddress 5A DATA BYTE CHPS DESCRIPTION phase of encoded colour subcarrier (including burst) relative to horizontal sync; can be adjusted in steps of 360/256 degrees VALUE 3FH 69H 67H 89H Cb, Cr data are two's complement Cb, Cr data are straight binary; default after reset Y data is two's complement Y data is straight binary; default after reset DESCRIPTION
SAA7120; SAA7121
horizontal and vertical trigger is taken from RCV2 and RCV1 respectively; default after reset horizontal and vertical trigger is decoded out of "CCIR 656" compatible data at MP port data from input ports is encoded; default after reset colour bar with fixed colours is encoded
RESULT PAL-B/G and data from input ports PAL-B/G and data from look-up table NTSC-M and data from input ports NTSC-M and data from look-up table
Remark: in subaddresses 5B, 5C, 5D, 5E and 62 all IRE values are rounded up. Table 13 Subaddress 5B and 5D DATA BYTE GAINU DESCRIPTION variable gain for Cb signal; input representation accordance with "CCIR 601" CONDITIONS white-to-black = 92.5 IRE GAINU = 0 GAINU = 118 (76H) white-to-black = 100 IRE GAINU = 0 GAINU = 125 (7DH) Table 14 Subaddress 5C and 5E DATA BYTE GAINV DESCRIPTION variable gain for Cr signal; input representation accordance with "CCIR 601" CONDITIONS white-to-black = 92.5 IRE GAINV = 0 GAINV = 165 (A5H) white-to-black = 100 IRE GAINV = 0 GAINV = 175 (AFH) REMARKS GAINV = -1.55 x nominal to +1.55 x nominal output subcarrier of V contribution = 0 output subcarrier of V contribution = nominal GAINV = -1.46 x nominal to +1.46 x nominal output subcarrier of V contribution = 0 output subcarrier of V contribution = nominal REMARKS GAINU = -2.17 x nominal to +2.16 x nominal output subcarrier of U contribution = 0 output subcarrier of U contribution = nominal GAINU = -2.05 x nominal to +2.04 x nominal output subcarrier of U contribution = 0 output subcarrier of U contribution = nominal
1997 Jan 06
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Philips Semiconductors
Preliminary specification
Digital Video Encoder (ConDENC)
Table 15 Subaddress 5D DATA BYTE BLCKL DESCRIPTION CONDITIONS
SAA7120; SAA7121
REMARKS recommended value: BLCKL = 42 (2AH) output black level = 34 IRE output black level = 54 IRE recommended value: BLCKL = 35 (23H) output black level = 32 IRE output black level = 52 IRE disable odd/even field control bit from RTCI enable odd/even field control bit from RTCI (see Fig.10)
variable black level; input white-to-sync = 140 IRE(1) representation BLCKL = 0 accordance with BLCKL = 63 (3FH) "CCIR 601" white-to-sync = 143 IRE(2) BLCKL = 0 BLCKL = 63 (3FH)
DECOE
real time control
logic 0 logic 1
Notes 1. Output black level/IRE = BLCKL x 2/6.29 + 34.0 2. Output black level/IRE = BLCKL x 2/6.18 + 31.7 Table 16 Subaddress 5E DATA BYTE BLNNL DESCRIPTION variable blanking level CONDITIONS white-to-sync = 140 BLNNL = 0 BLNNL = 63 (3FH) white-to-sync = 143 BLNNL = 0 BLNNL = 63 (3FH) DECPH real time control logic 0 logic 1 Notes 1. Output black level/IRE = BLNNL x 2/6.29 + 25.4 2. Output black level/IRE = BLNNL x 2/6.18 + 25.9 Table 17 Subaddress 5F DATA BYTE BLNVB CCRS DESCRIPTION variable blanking level during vertical blanking interval is typically identical to value of BLNNL select cross colour reduction filter in luminance; see Table 18 IRE(2) IRE(1) REMARKS recommended value: BLNNL = 46 (2EH) output blanking level = 25 IRE output blanking level = 45 IRE recommended value: BLNNL = 53 (35H) output blanking level = 26 IRE output blanking level = 46 IRE disable subcarrier phase reset bit from RTCI enable subcarrier phase reset bit from RTCI (see Fig.10)
Table 18 Logic levels and function of CCRS CCRS1 0 0 1 1 1997 Jan 06 CCRS0 0 1 0 1 DESCRIPTION no cross colour reduction; for overall transfer characteristic of luminance see Fig.3 cross colour reduction #1 active; for overall transfer characteristic see Fig.3 cross colour reduction #2 active; for overall transfer characteristic see Fig.3 cross colour reduction #3 active; for overall transfer characteristic see Fig.3 16
Philips Semiconductors
Preliminary specification
Digital Video Encoder (ConDENC)
Table 19 Subaddress 61 DATA BYTE FISE PAL SCBW LOGIC LEVEL 0 1 0 1 0 1 YGS INPI DOWN 0 1 0 1 0 1 Table 20 Subaddress 62H DATA BYTE RTCE LOGIC LEVEL 0 1 DESCRIPTION no real time control of generated subcarrier frequency 858 total pixel clocks per line NTSC encoding (non-alternating V component) DESCRIPTION 864 total pixel clocks per line; default after reset
SAA7120; SAA7121
PAL encoding (alternating V component); default after reset enlarged bandwidth for chrominance encoding (for overall transfer characteristic of chrominance in baseband representation see Figs 3 and 4) standard bandwidth for chrominance encoding (for overall transfer characteristic of chrominance in baseband representation see Figs 3 and 4); default after reset luminance gain for white - black 100 IRE; default after reset luminance gain for white - black 92.5 IRE including 7.5 IRE set-up of black PAL switch phase is nominal; default after reset PAL switch phase is inverted compared to nominal DACs for CVBS, Y and C in normal operational mode; default after reset DACs for CVBS, Y and C forced to lowest output voltage
real time control of generated subcarrier frequency through SAA7151B or SAA7111 (timing see Fig.10)
Table 21 Subaddress 62H DATA BYTE BSTA DESCRIPTION amplitude of colour burst; input representation in accordance with "CCIR 601" CONDITIONS white-to-black = 92.5 IRE; burst = 40 IRE; NTSC encoding BSTA = 0 to 2.02 x nominal white-to-black = 92.5 IRE; burst = 40 IRE; PAL encoding BSTA = 0 to 2.82 x nominal white-to-black = 100 IRE; burst = 43 IRE; NTSC encoding BSTA = 0 to 1.90 x nominal white-to-black = 100 IRE; burst = 43 IRE; PAL encoding BSTA = 0 to 3.02 x nominal recommended value: BSTA = 47 (2FH) recommended value: BSTA = 67 (43H) recommended value: BSTA = 45 (2DH) REMARKS recommended value: BSTA = 63 (3FH)
1997 Jan 06
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Philips Semiconductors
Preliminary specification
Digital Video Encoder (ConDENC)
Table 22 Subaddress 63 to 66 (four bytes to program subcarrier frequency) DATA BYTE DESCRIPTION CONDITIONS
SAA7120; SAA7121
REMARKS FSC3 = most significant byte FSC0 = least significant byte
FSC0 to FSC3 ffsc = subcarrier frequency (in f fsc 32 FSC = ------- x 2 , multiples of line frequency); f llc fllc = clock frequency (in multiples rounded up; see note 1 of line frequency) Note 1. Examples: a) NTSC-M: ffsc = 227.5, fllc = 1716 FSC = 569408543 (21F07C1FH). b) PAL-B/G: ffsc = 283.7516, fllc = 1728 FSC = 705268427 (2A098ACBH). Table 23 Subaddress 67 to 6A DATA BYTE L21O0 L21O1 L21E0 L21E1 DESCRIPTION first byte of captioning data, odd field second byte of captioning data, odd field first byte of extended data, even field second byte of extended data, even field
REMARKS LSBs of the respective bytes are encoded immediately after run-in and framing code, the MSBs of the respective bytes have to carry the parity bit, in accordance with the definition of Line 21 encoding format.
Table 24 Subaddress 6B DATA BYTE PRCV2 LOGIC LEVEL 0 1 ORCV2 CBLF 0 1 0 DESCRIPTION polarity of RCV2 as output is active HIGH, rising edge is taken when input, respectively; default after reset polarity of RCV2 as output is active LOW, falling edge is taken when input, respectively pin RCV2 is switched to input; default after reset pin RCV2 is switched to output if ORCV2 = HIGH, pin RCV2 provides an HREF signal (Horizontal Reference pulse that is defined by RCV2S and RCV2E, also during vertical blanking Interval); default after reset if ORCV2 = LOW and bit SYMP = LOW, signal input to RCV2 is used for horizontal synchronization only (if TRCV2 = 1); default after reset 1 if ORCV2 = HIGH, pin RCV2 provides a `Composite-Blanking-Not' signal, for example a reference pulse that is defined by RCV2S and RCV2E, excluding Vertical Blanking Interval, which is defined by FAL and LAL if ORCV2 = LOW and bit SYMP = LOW, signal input to RCV2 is used for horizontal synchronization (if TRCV2 = 1) and as an internal blanking signal PRCV1 ORCV1 TRCV2 0 1 0 1 0 1 SRCV1 1997 Jan 06 - polarity of RCV1 as output is active HIGH, rising edge is taken when input; default after reset polarity of RCV1 as output is active LOW, falling edge is taken when input pin RCV1 is switched to input; default after reset pin RCV1 is switched to output horizontal synchronization is taken from RCV1 port (at bit SYMP = LOW) or from decoded frame sync of "CCIR 656" input (at bit SYMP = HIGH); default after reset horizontal synchronization is taken from RCV2 port (at bit SYMP = LOW) defines signal type on pin RCV1; see Table 25 18
Philips Semiconductors
Preliminary specification
Digital Video Encoder (ConDENC)
Table 25 Logic levels and function of SRCV1 DATA BYTE AS OUTPUT SRCV11 0 0 1 1 SRCV10 0 1 0 1 VS FS FSEQ not applicable VS FS FSEQ AS INPUT
SAA7120; SAA7121
FUNCTION vertical sync each field; default after reset frame sync (odd/even) field sequence, vertical sync every fourth field (PAL = 0) or eighth field (PAL = 1)
not applicable -
Table 26 Subaddress 6C and 6D DATA BYTE HTRIG DESCRIPTION sets the horizontal trigger phase related to signal on RCV1 or RCV2 input values above 1715 (FISE = 1) or [1727 (FISE = 0)] are not allowed increasing HTRIG decreases delays of all internally generated timing signals reference mark: analog output horizontal sync (leading slope) coincides with active edge of RCV used for triggering at HTRIG = 398H [398H] Table 27 Subaddress 6D DATA BYTE VTRIG DESCRIPTION sets the vertical trigger phase related to signal on RCV1 input increasing VTRIG decreases delays of all internally generated timing signals, measured in half lines variation range of VTRIG = 0 to 31 (1FH) Table 28 Subaddress 6E DATA BYTE SBLBN PHRES FLC LOGIC LEVEL 0 1 - - DESCRIPTION vertical blanking is defined by programming of FAL and LAL; default after reset vertical blanking is forced in accordance with "CCIR 624" (50 Hz) or RS170A (60 Hz) selects the phase reset mode of the colour subcarrier generator; see Table 29 field length control; see Table 30
Table 29 Logic levels and function of PHRES DATA BYTE DESCRIPTION PHRES1 0 0 1 1 PHRES0 0 1 0 1 no reset or reset via RTCI from SAA7111 if bit RTCE = 1; default after reset reset every two lines reset every eight fields reset every four fields
1997 Jan 06
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Philips Semiconductors
Preliminary specification
Digital Video Encoder (ConDENC)
Table 30 Logic levels and function of FLC DATA BYTE DESCRIPTION FLC1 0 0 1 1 FLC0 0 1 0 1
SAA7120; SAA7121
interlaced 312.5 lines/field at 50 Hz, 262.5 lines/field at 60 Hz; default after reset non-interlaced 312 lines/field at 50 Hz, 262 lines/field at 60 Hz non-interlaced 313 lines/field at 50 Hz, 263 lines/field at 60 Hz non-interlaced 313 lines/field at 50 Hz, 263 lines/field at 60 Hz
Table 31 Subaddress 6F DATA BYTE CCEN TTXEN SCCLN LOGIC LEVEL - 0 1 - disables teletext insertion enables teletext insertion selects the actual line, where closed caption or extended data are encoded line = (SCCLN + 4) for M-systems line = (SCCLN + 1) for other systems Table 32 Logic levels and function of CCEN DATA BYTE DESCRIPTION CCEN1 0 0 1 1 CCEN0 0 1 0 1 Line 21 encoding off enables encoding in field 1 (odd) enables encoding in field 2 (even) enables encoding in both fields DESCRIPTION enables individual Line 21 encoding; see Table 32
Table 33 Subaddress 70 to 72 DATA BYTE RCV2S start of output signal on pin RCV2 values above 1715 (FISE = 1) or [1727 (FISE = 0)] are not allowed first active pixel at analog outputs (corresponding input pixel coinciding with RCV2) at RCV2S = 11AH [0FDH] RCV2E end of output signal on pin RCV2 values above 1715 (FISE = 1) or [1727 (FISE = 0)] are not allowed last active pixel at analog outputs (corresponding input pixel coinciding with RCV2) at RCV2E = 694H [687H] DESCRIPTION
1997 Jan 06
20
Philips Semiconductors
Preliminary specification
Digital Video Encoder (ConDENC)
Table 34 Subaddress 73 and 74 DATA BYTE TTXHS TTXHD start of signal on pin TTXRQ see Fig.7 DESCRIPTION
SAA7120; SAA7121
indicates the delay in clock cycles between rising edge of TTXRQ output and valid data on pin TTX minimum value has to be TTXHD = 2
Table 35 Subaddress 75 DATA BYTE VS_S DESCRIPTION Vertical Sync. shift between RCV1 and RCV2 (switched to output) in master mode it is possible to shift H-sync (RCV2; CBLF = 0) against V-sync (RCV1; SRCV1 = 00) standard value: VS_S = 3 Table 36 Subaddress 76, 77 and 7C DATA BYTE TTXOVS line = (TTXOVS + 4) for M-systems line = (TTXOVS + 1) for other systems TTXOVE last line of occurrence of signal on pin TTXRQ in odd field line = (TTXOVE + 3) for M-systems line = TTXOVE for other systems Table 37 Subaddress 78, 79 and 7C DATA BYTE TTXEVS line = (TTXEVS + 4) for M-systems line = (TTXEVS + 1) for other systems TTXEVE last line of occurrence of signal on pin TTXRQ in even field line = (TTXEVE + 3) for M-systems line = TTXEVE for other systems Table 38 Subaddress 7C DATA BYTE TTX60 LOGIC LEVEL 0 1 DESCRIPTION enables NABTS (FISE = 1) or European TTX (FISE = 0); default after reset enables World Standard Teletext 60 Hz (FISE = 1) DESCRIPTION first line of occurrence of signal on pin TTXRQ in even field DESCRIPTION first line of occurrence of signal on pin TTXRQ in odd field
Table 39 Subaddress 7A to 7C DATA BYTE FAL LAL DESCRIPTION first active line = FAL + 4 for M-systems, = FAL + 1 for other systems, measured in lines FAL = 0 coincides with the first field synchronization pulse last active line = LAL + 3 for M-systems, = LAL for other system, measured in lines LAL = 0 coincides with the first field synchronization pulse 21
1997 Jan 06
Philips Semiconductors
Preliminary specification
Digital Video Encoder (ConDENC)
Table 40 Subaddress 7E and 7F DATA BYTE LINE DESCRIPTION
SAA7120; SAA7121
individual lines in both fields (PAL counting) can be disabled for insertion of teletext by the respective bits, disabled line = LINExx (50 Hz field rate) this bit mask is effective only, if the lines are enabled by TTXOVS/TTXOVE and TTXEVS/TTXEVE
Slave Transmitter Table 41 Slave transmitter (slave address 89H or 8DH) REGISTER FUNCTION Status byte DATA BYTE SUBADDRESS D7 - VER2 D6 VER1 D5 VER0 D4 D3 D2 0 D1 FSEQ D0 O_E CCRDO CCRDE
Table 42 No subaddress DATA BYTE VER CCRDO LOGIC LEVEL - 1 0 CCRDE 1 0 FSEQ O_E 1 0 1 0 DESCRIPTION Version identification of the device. It will be changed with all versions of the device that have different programming models. Current version is 000 binary. Closed caption bytes of the odd field have been encoded. The bit is reset after information has been written to the subaddresses 67 and 68. It is set immediately after the data has been encoded. Closed caption bytes of the even field have been encoded. The bit is reset after information has been written to the subaddresses 69 and 6A. It is set immediately after the data has been encoded. During first field of a sequence (repetition rate: NTSC = 4 fields, PAL = 8 fields). Not first field of a sequence. During even field. During odd field.
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Philips Semiconductors
Preliminary specification
Digital Video Encoder (ConDENC)
CHARACTERISTICS VDDD = 3.0 to 3.6 V; Tamb = 0 to +70 C; unless otherwise specified. SYMBOL Supply VDDA VDDD IDDA IDDD Inputs VIL VIH ILI Ci LOW level input voltage (except SDA, SCL, AP, SP and XTALI) HIGH level input voltage (except, SDA, SCL, AP, SP and XTALI) input leakage current input capacitance clocks data Outputs VOL VOH LOW level output voltage (except SDA and XTALO) HIGH level output voltage (except, SDA, and XTALO) IOL = 4 mA IOH = 4 mA analog supply voltage digital supply voltage analog supply current digital supply current note 1 note 1 PARAMETER CONDITIONS
SAA7120; SAA7121
MIN.
MAX.
UNIT
3.1 3.0 - - -0.5 2.0 - - -
3.5 3.6 62 38
V V mA mA
+0.8 VDDD + 0.3 1 10 8 8
V V A pF pF pF
I/Os at high impedance - - VDDD - 4
0.4 -
V V
I2C-bus; SDA and SCL VIL VIH Ii VOL Io TLLC tr tf tSU;DAT tHD;DAT LOW level input voltage HIGH level input voltage input current LOW level output voltage (SDA) output current Vi = LOW or HIGH IOL = 3 mA during acknowledge -0.5 2.3 -10 - 3 VDDD + 0.3 VDDD + 0.3 +10 0.4 - V V A V mA
Clock timing (LLC) cycle time duty factor tHIGH/tLLC rise time fall time note 2 note 3 note 2 note 2 34 40 - - 41 60 5 6 - - ns % ns ns
Input timing input data set-up time (any pin except SCL, SDA, RESET, AP and SP) input data hold time (any pin except SCL, SDA, RESET, AP and SP) 6 3 ns ns
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Philips Semiconductors
Preliminary specification
Digital Video Encoder (ConDENC)
SAA7120; SAA7121
SYMBOL Crystal oscillator fn f/fn Tamb CL RS C1 C0 CL th td Vo(p-p) Rint RL B-3dB ILE DLE Notes
PARAMETER
CONDITIONS -
MIN.
MAX.
UNIT
nominal frequency (usually 27 MHz) permissible deviation of nominal frequency
3rd harmonic note 4
30
MHz
-50 x 10-6 +50 x 10-6 0 8 - 1.5 - 20% 3.5 - 20% 70 - 80 1.5 + 20% 3.5 + 20% C pF fF pF
CRYSTAL SPECIFICATION operating ambient temperature load capacitance series resistance motional capacitance (typical) parallel capacitance (typical)
Data and reference signal output timing output load capacitance output hold time output delay time 7.5 4 - 40 - 25 pF ns ns
C, Y and CVBS outputs output signal voltage (peak-to-peak value) internal serial resistance output load resistance output signal bandwidth of DACs LF integral linearity error of DACs LF differential linearity error of DACs note 5 1.20 1 75 10 - - 1.45 3 300 - 3 1 V MHz LSB LSB
1. At maximum supply voltage with highly active input signals. 2. The data is for both input and output direction. 3. With LLC in input mode. In output mode, with a crystal connected to XTALO/XTALI duty factor is typically 50%. 4. If an internal oscillator is used, crystal deviation of nominal frequency is directly proportional to the deviation of subcarrier frequency and line/field frequency. 5. For full digital range, without load, VDDA = 3.3 V. The typical voltage swing is 1.35 V, the typical minimum output voltage (digital zero at DAC) is 0.2 V.
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Philips Semiconductors
Preliminary specification
Digital Video Encoder (ConDENC)
SAA7120; SAA7121
handbook, full pagewidth
tHIGH
TLLC 2.6 V 1.5 V 0.6 V
LLC clock output tHD; DAT tHIGH LLC clock input tf TLLC tr
2.4 V 1.5 V 0.8 V tSU; DAT tHD; DAT tf tr 2.0 V
input data
valid td
not valid
valid 0.8 V
tHD; DAT output data valid
2.4 V not valid valid 0.6 V
MBE742
Fig.8 Clock data timing.
handbook, full pagewidth
LLC
MP(n)
Cb(0)
Y(0)
Cr(0)
Y(1)
Cb(2)
RCV2
MGB699
The data demultiplexing phase is coupled to the internal horizontal phase. The phase of the RCV2 signal is programmed to tbf (tbf for 50 Hz) in this example in output mode (RCV2S).
Fig.9 Functional timing.
1997 Jan 06
25
Philips Semiconductors
Preliminary specification
Digital Video Encoder (ConDENC)
SAA7120; SAA7121
handbook, full pagewidth
H/L transition count start LOW 128
13
4 bits reserved (7) HPLL increment
0 21
5 bits reserved (7)
(3)
(4) (5)
(6)
FSCPLL increment (1)
0
(2)
RTCI time slot: 0 1
14 19 67 69 72 74 68
not used in SAA7120/21
valid sample
invalid sample
8/LLC
MBH789
(1) SAA7111 provides (22:0) bits, resulting in 3 reserved bits before sequence bit. (2) Sequence bit PAL: 0 = (R-Y) line normal, 1 = (R-Y) line inverted NTSC: 0 = no change.
(3) (4) (5) (6) (7)
Reset bit: only from SAA7111 decoder. FISE bit: 0 = 50 Hz, 1 = 60 Hz. Odd/even bit: odd/even from external. Colour detection: 0 = no colour detected, 1 = colour detected. Reserved bits: 232 with 50 Hz systems, 229 with 60 Hz systems.
Fig.10 RTCI timing.
Explanation of RTCI data bits 1. The ConDENC generates the subcarrier frequency out of the FSCPLL increment if enabled (see item 6.). 2. The PAL bit indicates the line with inverted R - Y component of colour difference signal. 3. If the reset bit is enabled (RTCE = 1; DECPH = 1; PHRES = 00), the phase of the subcarrier is reset in each line whenever the reset bit of RTCI input is set to 1. 4. If the FISE bit is enabled (RTCE = 1; DECFIS = 1), the ConDENC takes this bit instead of the FISE bit in subaddress 61H. 5. If the odd/even bit is enabled (RTCE = 1; DECOE = 1), the ConDENC ignores its internally generated odd/even flag and takes the odd/even bit from RTCI input.
6. If the colour detection bit is enabled (RTCE = 1; DECCOL = 1) and no colour was detected (colour detection bit = 0), the subcarrier frequency is generated by the ConDENC. In the other case (colour detection bit = 1) the subcarrier frequency is evaluated out of FSCPLL increment. If the colour detection bit is disabled (RTCE = 1; DECCOL = 0), the subcarrier frequency is evaluated out of FSCPLL increment, independent of the colour detection bit of RTCI input.
1997 Jan 06
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SAA7120; SAA7121
Preliminary specification
Fig.11 Application environment of ConDENC.
handbook, full pagewidth
1997 Jan 06
+3.3 V digital supply 0.1 F AGND 0.1 F DGND 0.1 F AGND VDDD1, VDDD2, VDDD3 VDDA1 25 2 (1) 30 CVBS 75 2 (1) 27 10 Y 75 4.7 UCVBS 1.23 V (p-p)(2) AGND 28 31 6, 17, 39 use one capacitor for each VDDD DAC1 36 VDDA4 VDDA2 VDDA3 AGND 0.1 F AGND 0.1 F +3.3 V analog supply
Philips Semiconductors
DGND
0.1 H
10 pF
10 pF
APPLICATION INFORMATION
1 nF
27.0 MHz X1(3)
3rd harmonic
XTALI
XTALO
Digital Video Encoder (ConDENC)
35
34
27
DAC2
UY 1.00 V (p-p)(2) 24 C 10 AGND
digital inputs and outputs
SAA7120/21
DAC3 2 (1)
75
UC 0.62 V (p-p)(2) AGND
5, 18, 38 VSSD1, VSSD2, VSSD3 DGND
32, 33 VSSA1, VSSA2 AGND
MBH786
(1) Typical value. (2) For 100/100 colour bar. (3) Order no. 4312 065 02341.
Philips Semiconductors
Preliminary specification
Digital Video Encoder (ConDENC)
PACKAGE OUTLINE
SAA7120; SAA7121
QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm
SOT307-2
c
y X
A 33 34 23 22 ZE
e Q E HE wM bp pin 1 index 44 1 bp D HD wM 11 ZD B vM B vMA 12 detail X A A2 A1 (A 3) Lp L
e
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2.10 A1 0.25 0.05 A2 1.85 1.65 A3 0.25 bp 0.40 0.20 c 0.25 0.14 D (1) 10.1 9.9 E (1) 10.1 9.9 e 0.8 HD 12.9 12.3 HE 12.9 12.3 L 1.3 Lp 0.95 0.55 Q 0.85 0.75 v 0.15 w 0.15 y 0.1 Z D (1) Z E (1) 1.2 0.8 1.2 0.8 10 0o
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT307-2 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 92-11-17 95-02-04
1997 Jan 06
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Philips Semiconductors
Preliminary specification
Digital Video Encoder (ConDENC)
SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). Reflow soldering Reflow soldering techniques are suitable for all QFP packages. The choice of heating method may be influenced by larger plastic QFP packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our "Quality Reference Handbook" (order code 9397 750 00192). Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. Wave soldering Wave soldering is not recommended for QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices.
SAA7120; SAA7121
If wave soldering cannot be avoided, the following conditions must be observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. Even with these conditions, do not consider wave soldering the following packages: QFP52 (SOT379-1), QFP100 (SOT317-1), QFP100 (SOT317-2), QFP100 (SOT382-1) or QFP160 (SOT322-1). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
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Philips Semiconductors
Preliminary specification
Digital Video Encoder (ConDENC)
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
SAA7120; SAA7121
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
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Philips Semiconductors
Preliminary specification
Digital Video Encoder (ConDENC)
NOTES
SAA7120; SAA7121
1997 Jan 06
31
Philips Semiconductors - a worldwide company
Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 1 60 101, Fax. +43 1 60 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 689 211, Fax. +359 2 689 102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S, Tel. +45 32 88 2636, Fax. +45 31 57 1949 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615800, Fax. +358 9 61580/xxx France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex, Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427 Germany: Hammerbrookstrae 69, D-20097 HAMBURG, Tel. +49 40 23 53 60, Fax. +49 40 23 536 300 Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS, Tel. +30 1 4894 339/239, Fax. +30 1 4814 240 Hungary: see Austria India: Philips INDIA Ltd, Shivsagar Estate, A Block, Dr. Annie Besant Rd. Worli, MUMBAI 400 018, Tel. +91 22 4938 541, Fax. +91 22 4938 722 Indonesia: see Singapore Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3, 20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA, Tel. +48 22 612 2831, Fax. +48 22 612 2327 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000, Tel. +27 11 470 5911, Fax. +27 11 470 5494 South America: Rua do Rocio 220, 5th floor, Suite 51, 04552-903 Sao Paulo, SAO PAULO - SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 829 1849 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 3 301 6312, Fax. +34 3 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 632 2000, Fax. +46 8 632 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. +41 1 488 2686, Fax. +41 1 481 7730 Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2870, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Talatpasa Cad. No. 5, 80640 GULTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 625 344, Fax.+381 11 635 777
For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1997
Internet: http://www.semiconductors.philips.com
SCA53
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
657021/1200/01/pp32
Date of release: 1997 Jan 06
Document order number:
9397 750 01378

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